Error-correction encoding method and device, and decoding method and device using channel polarization

ABSTRACT

[Solution] In an encoding device, the information bit sequence is input on division for each designated bit length; error-correction encoding is performed on an information block of the designated bit length to generate L M-bit codes, each M-bit code having a predetermined bit length M; the L M-bit codes are converted into M L-bit blocks each having a predetermined bit length of L; the M L-bit blocks are Polar-converted to M L-bit codes, each L-bit code having a bit length of L, through channel polarization processing; and division of the information bit sequence is determined based on channel polarization information.

The present invention relates to encoding/decoding techniques capable ofcorrecting bit errors occurring in digital data, and more particularlyto an encoding/decoding technique using channel polarization.

BACKGROUND ART

In operations of digital data communication systems and memory systems,it is necessary to take measures against bit errors that may occur dueto various factors. Error-correction encoding, which is a typicaltechnique thereof, makes it possible to correct bit errors bycalculating redundant data from a data sequence through predeterminedcalculation and adding it to the data sequence. For example, PatentLiteratures 1 and 2 disclose an error-correction encoding techniquewhich improves the encoding gain by dividing an information bit sequenceusing the property of a low-density parity check code. The bit-errortolerance of the error-correction encoding system depends on redundancyand the statistical property of a transmission channel.

A Polar encoding technique using channel polarization has been known asa system having the highest bit-error tolerance (Non-Patent Literature1). Channel polarization is to polarize multiple channels into highlyreliable channels with high error tolerance and channels with low errortolerance by linear conversion of channels. Using channels with higherror tolerance enables highly reliable information communication. ThePolar encoding technique can guarantee the error tolerance reaching thetheoretical limit by setting the frame length extremely long. Further,in the case of a frame length of about several thousands of bits, byapplying the SC-List decoding method (Non-Patent Literature 2) to thePolar encoding technique, it is possible to achieve a highererror-correction capability than other encoding techniques. Further,Patent Literature 3 discloses a rate matching technique for Polar codesand provides a means for generating Polar codes having different framelengths from a single Polar code in accordance with the systemrequirements.

Further, as a technique for suppressing the decoding latency in thePolar encoding technique, a Simplified SC (SSC) decoding method has beenproposed by which the SC decoding method can be simplified by selectingcalculations that can be removed (Non-Patent Literature 3).

PRIOR ART LITERATURE Patent Literature [Patent Literature 1]

-   WO2010/073922 Pamphlet

[Patent Literature 2]

-   Wo2007/132656 Pamphlet

[Patent Literature 3]

-   JP 2017-512004

Non-Patent Literature [Non-Patent Literature 1]

-   E. Arikan, “Channel polarization: A method for constructing    capacity-achieving codes for symmetric binary-input memoryless    channels,” IEEE Transactions on Information Theory, vol. 55, no. 7,    pp. 3051-3073, July 2009.

[Non-Patent Literature 2]

-   I. Tal and A. Vardy, “List decoding of polar codes,” IEEE    Transactions on Information Theory, vpl. 61, no. 5, pp. 2213-2226,    May 2015.

[Non-Patent Literature 3]

-   A. A. A. D. Yazdi and F. R. Kschischang, “A simplified    successive-cancellation decoder for polar codes”, IEEE    Communications Letters, vol. 15, no. 2, pp. 1378-1380, December    2011.

DISCLOSURE OF INVENTION Problems to be Solved by Invention

A problem in the Polar encoding technique is the difficulty in enhancingthe speed of the decoding process.

For instance, according to the Successive-Cancellation decoding method(hereinafter abbreviated as SC decoding method) presented in Non-PatentLiterature 1, error-correction processing is sequentially performed on abit-by-bit basis from the beginning, resulting in theoretical difficultyin increasing the speed through parallel processing. Accordingly, thePolar encoding technique has an advantage that the longer the framelength, the higher the bit error tolerance, but has a disadvantage thatthe longer the frame length, the longer processing latency due todifficulty in parallelization of decoding processing.

Further, in the SC-List decoding method which is particularly effectivein the case of frame lengths of about several thousand bits or less, anincrease in processing delay due to difficulty in parallel processingbecomes more and more significant.

Further, in the above-mentioned SSC decoding method, the selection ofprocessing calculations that can be removed in the SC decoding methoddepends on the configuration method of the Polar code and the settingparameters such as coding rate. Accordingly, it is difficult to applythe SSC decoding method to a system that requires a wide range ofparameter settings according to changes in communication conditions.Recently, due to growing in transmission capacity, a system thatadaptively changes the coding rate and the number of values inmultilevel modulation according to the communication channel situationhas become the mainstream, so that it becomes more and more difficult toapply the SSC decoding method.

Therefore, the present invention is intended to solve the aboveproblems, and an object thereof is to provide encoding and decodingtechniques capable of speeding up an error-correction decoding processutilizing channel polarization.

Solution

According to a first aspect of the present invention, an encoding devicethat encodes an information bit sequence blocked into blocks of aconstant bit length K to generate a code bit sequence of a constant bitlength M×L, includes: an error-correction encoding means that inputs theinformation bit sequence on division for each designated bit lengthaccording to an information-bit length switching signal and performserror-correction encoding on an information block of the designated bitlength to generate L M-bit codes, each M-bit code having a predeterminedbit length M; a block length conversion means that converts the L M-bitcodes into M L-bit blocks each having a predetermined bit length of L byreordering bits of the L M-bit codes; a Polar conversion means thatconverts the M L-bit blocks to M L-bit codes, each L-bit code having abit length of L, through channel polarization processing to output aconverted M×L-bit code as the code bit sequence; and an information bitlength switching means that generates the information bit lengthswitching signal for dividing the information bit sequence into Ldesignated bit lengths which are not necessarily constant, based onchannel polarization information of the Polar conversion means.

According to a second aspect of the present invention, a decoding devicethat inputs an input signal sequence and estimates an information bitsequence from the input signal sequence, the input signal sequencecorresponding to a code bit sequence of a constant bit length M×L,wherein an encoding device generates the code bit sequence througherror-correction encoding and channel polarization processing on aninformation bit sequence of a constant bit length K, includes: M Polardecoding means that divides the input signal sequence into M inputsignal blocks, each input signal block including L input signals,performs the channel polarization processing on each of the M inputsignal blocks, and outputs L Polar decoded signals for each of the Minput signal blocks; an error-correction decoding means that inputs aPolar decoded signal according to a designated bit length designated byan information bit length switching signal, from M Polar decoded signalblocks, each Polar decoded signal block including L Polar decodedsignals which are output respectively by the M Polar decoding means, andestimates the information bit sequence according to error-correctiondecoding scheme; and an information bit length switching means thatgenerates the information bit length switching signal for designating,as the designated bit length, an information bit length included in theM Polar decoded signal blocks output respectively by the M Polardecoding means.

According to a third aspect of the present invention, an encoding methodfor encoding an information bit sequence blocked into blocks of aconstant bit length K to generate a code bit sequence of a constant bitlength M×L, includes: by an error-correction encoding means, inputtingthe information bit sequence on division for each designated bit lengthaccording to an information-bit length switching signal and performingerror-correction encoding on an information block of the designated bitlength to generate L M-bit codes, each M-bit code having a predeterminedbit length M; by a block length conversion means, converting the L M-bitcodes into M L-bit blocks each having a predetermined bit length of L byreordering bits of the L M-bit codes; by a Polar conversion means,converting the M L-bit blocks to M L-bit codes, each L-bit code having abit length of L, through channel polarization processing to output aconverted M×L-bit code as the code bit sequence; and by an informationbit length switching means, generating the information bit lengthswitching signal for dividing the information bit sequence into Ldesignated bit lengths which are not necessarily constant, based onchannel polarization information of the Polar conversion means.

According to a fourth aspect of the present invention, a decoding methodfor inputting an input signal sequence and estimating an information bitsequence from the input signal sequence, the input signal sequencecorresponding to a code bit sequence of a constant bit length M×L,wherein an encoding device generates the code bit sequence througherror-correction encoding and channel polarization processing on aninformation bit sequence of a constant bit length K, includes: by MPolar decoding means, dividing the input signal sequence into M inputsignal blocks, each input signal block including L input signals,performing the channel polarization processing on each of the M inputsignal blocks, and outputting L Polar decoded signals for each of the Minput signal blocks; by an error-correction decoding means, inputting aPolar decoded signal according to a designated bit length designated byan information bit length switching signal, from M Polar decoded signalblocks, each Polar decoded signal block including L Polar decodedsignals which are output respectively by the M Polar decoding means, andestimating the information bit sequence according to error-correctiondecoding scheme; and by an information bit length switching means,generating the information bit length switching signal for designating,as the designated bit length, an information bit length included in theM Polar decoded signal blocks output respectively by the M Polardecoding means.

According to a fifth aspect of the present invention, a program thatcauses a computer to function as an encoding device that encodes aninformation bit sequence blocked into blocks of a constant bit length Kto generate a code bit sequence of a constant bit length M×L, includes:an error-correction encoding function of inputting the information bitsequence on division for each designated bit length according to aninformation-bit length switching signal and performs error-correctionencoding on an information block of the designated bit length togenerate L M-bit codes, each M-bit code having a predetermined bitlength M; a block length conversion function of converting the L M-bitcodes into M L-bit blocks each having a predetermined bit length of L byreordering bits of the L M-bit codes; a Polar conversion function ofconverting the M L-bit blocks to M L-bit codes, each L-bit code having abit length of L, through channel polarization processing to output aconverted M×L-bit code as the code bit sequence; and an information bitlength switching function of generating the information bit lengthswitching signal for dividing the information bit sequence into Ldesignated bit lengths which are not necessarily constant, based onchannel polarization information of the Polar conversion means.

According to a sixth aspect of the present invention, a program thatcauses a computer to function as an decoding device that inputs an inputsignal sequence and estimates an information bit sequence from the inputsignal sequence, the input signal sequence corresponding to a code bitsequence of a constant bit length M×L, wherein an encoding devicegenerates the code bit sequence through error-correction encoding andchannel polarization processing on an information bit sequence of aconstant bit length K, includes: M Polar decoding functions of dividingthe input signal sequence into M input signal blocks, each input signalblock including L input signals, of performing the channel polarizationprocessing on each of the M input signal blocks, and of outputting LPolar decoded signals for each of the M input signal blocks; anerror-correction decoding function of inputting a Polar decoded signalaccording to a designated bit length designated by an information bitlength switching signal, from M Polar decoded signal blocks, each Polardecoded signal block including L Polar decoded signals which are outputrespectively by the M Polar decoding means, and estimating theinformation bit sequence according to error-correction decoding scheme;and an information bit length switching function of generating theinformation bit length switching signal for designating, as thedesignated bit length, an information bit length included in the M Polardecoded signal blocks output respectively by the M Polar decoding means.

Advantages of Invention

According to the present invention, high error-correction capabilityutilizing channel polarization is guaranteed, and high-speed processingis possible. Furthermore, switching error-correction encoders accordingto a designated bit length enables high-speed processing even in thecase of setting a wide range of coding rates.

BRIEF DESCRIPTIONS OF DRAWINGS

FIG. 1 is a diagram showing an example of a system configuration towhich an encoding and decoding method according to the present inventionis applied.

FIG. 2 is a block diagram showing a schematic configuration of anencoding device and a decoding device according to an embodiment of thepresent invention.

FIG. 3 is a block diagram showing a configuration example of a variableinformation-length encoder in the encoding device shown in FIG. 2.

FIG. 4 is a block diagram showing a configuration example of an encoderin the variable information-length encoder shown in FIG. 3.

FIG. 5 is a bit array diagram showing an example of a conversion methodof the block length converter in the encoding device shown in FIG. 2.

FIG. 6 is a block diagram showing a configuration example of a Polarconverter in the encoding device shown in FIG. 2.

FIG. 7 is a block diagram showing a configuration example of aninformation-length switching designation section in the encoding deviceshown in FIG. 2.

FIG. 8 is a block diagram showing a configuration example of a variableinformation-length decoder in the decoding device shown in FIG.

FIG. 9 is a block diagram showing a configuration example of a decoderin the variable information-length decoder shown in FIG. 2.

FIG. 10 is a diagram showing an example of a bit sequence for explainingthe encoding method in the encoding device shown in FIG. 2.

FIG. 11 is a diagram showing an example of a bit sequence for explainingthe decoding method in the decoding device shown in FIG. 2.

FIG. 12 is a diagram showing an example of a code-trellis having aninformation bit length of 2 and a code bit length of 16.

FIG. 13 is a diagram showing an example of a code-trellis having aninformation bit length of 4 and a code bit length of 16.

FIG. 14 is a diagram showing an example of a code-trellis having aninformation bit length of 5 and a code bit length of 16.

FIG. 15 is a diagram showing an example of a code-trellis having aninformation bit length of 11 and a code bit length of 16.

FIG. 16 is a diagram showing an example of a code-trellis having aninformation bit length of 12 and a code bit length of 16.

FIG. 17 is a diagram showing an example of a code-trellis having aninformation bit length of 14 and a code bit length of 16.

FIG. 18 is a block diagram showing a schematic configuration of a dataprocessing device having the same function as the encoding device and/orthe decoding device according to another embodiment of the presentinvention.

EMBODIMENTS OF INVENTION Summary of Exemplary Embodiments

According to an exemplary embodiment of the present invention,information regarding channel polarization, for example, frozen bitposition information in the Polar encoding method is used to specify abit length of the information to be encoded. The information bitsequence to be encoded is divided according to each of designated bitlengths. By performing error-correction encoding based on theinformation bit blocks thus divided and then performing Polar coding, itis possible to parallelize the Polar decoding at the decoding side.Furthermore, by switching error-correction encoders according to thedesignated bit length of the information bits to be encoded, it becomesapplicable to a system that requires a wide range of parameter settingsaccording to changes in the communication status.

As illustrated in FIG. 1, an encoding device 100 and a decoding device200 according to an exemplary embodiment of the present invention can beapplied to communication systems via transmission channels or memorysystems via memory media. The coding apparatus 100 encodes a datasequence to generate a code sequence, and a signal corresponding to thecode sequence is transmitted through a transmission channel or stored ina memory or the like. The decoding device 200 estimates the originaldata sequence from the signal sequence received through the transmissionchannel or the signal sequence read from the memory.

In such a system, a bit error may occur in digital data due todisturbance such as noise during data transmission or data storage. Theencoding/decoding method according to the present exemplary embodimentcan correct such a bit error with high reliability and at high speed.Hereinafter, the exemplary embodiments of the present invention will bedescribed in detail with reference to the drawings. However, theconfigurations described in the following embodiments are described asexamples, and the technical scope of the present invention is notlimited thereto.

1. Configuration 1.1) System

It is assumed that an encoding device 100 and a decoding device 200illustrated in FIG. 2 constitute the encoding/decoding system as shownin FIG. 1.

The encoding apparatus 100 includes a variable information-lengthencoder 101, a block length converter 102, a Polar converter 103, and aninformation bit length switch 104. The variable information-lengthencoder 101 sequentially divides an information bit sequence of bitlength K according to L designated bit lengths (k₀, k₁, . . . , k_(L-1))provided from the information bit length switch 104 and then addsredundant bits to the divided information bit block ki (i=0, 1, . . . ,L−1) to generate a code of a constant bit length M. Accordingly, L isthe number of divisions of the information bit sequence, and the Ldesignated bit lengths k₀, k₁, . . . , k_(L-1) are not necessarily thesame length. Each value of k₀, k₁, . . . , k_(L-1) can be determineddepending on the channel polarization, specifically, depending on thefrozen bit position information of the Polar encoding, as describedlater. The numerical value L is set to a power of 2. The block lengthconverter 102, when inputting an M-bit code, converts the block lengthfrom M to L (details will be described later), and outputs a bitsequence of bit length L to the Polar converter 103. The Polar converter103 performs the linear conversion on a bit sequence of the bit length Land outputs a code bit sequence of a bit length N=M×L.

The decoding device 200 includes: M Polar decoders P-DEC(j) (j=0, 1, 2,. . . , M−1) arranged in parallel between the switch 201 and themultiplexer/demultiplexer 202; a variable information-length decoder 203connected to the multiplexer/demultiplexer 202; and an information bitlength switch 204 which provides a designated bit length (k₀, k₁, . . ., k_(L-1)) to the variable information-length decoder 203. The switch201 inputs a signal sequence corresponding to the code bit sequence ofthe bit length M×L output from the encoding device 100, divides thesignal sequence in signal sequence blocks corresponding to L-bit blocksof the code bit sequence, and sequentially outputs the signal sequenceblocks to M Polar decoders P-DEC(j). The multiplexer/demultiplexer 202receives signal sequences decoded respectively by the M Polar decodersP-DEC(j), and combines signals of the signal sequences in the same orderstarting the top of each signal sequence to output the combined signalsto the variable information-length decoder 203. The variableinformation-length decoder 203 receives the signals of the signalsequences from the M Polar decoders P-DEC (j), and feeds code bitscorresponding to the M signals respectively back to corresponding onesof the M Polar decoders P-DEC(j). Each Polar decoder P-DEC (j), whilereceiving a feedback code bit, performs decoding of the next inputsignal. Further, the variable information-length decoder 203 decodes theM-bit code by referring to the corresponding designated bit length togenerate information bit blocks k_(i), and sequentially selects them todecode the information bit sequence of the bit length K as decodedoutput. The functions of the information bit length switch 104 of theencoding device 100 and the information bit length switch 204 of thedecoding device 200 will be described later.

Hereinafter, the functional blocks that respectively configure theencoding device 100 and the decoding device 200 will be furtherdescribed.

1.2) Variable Information-Length Encoder

As illustrated in FIG. 3, the variable information-length encoder 101includes M+1 error-correction encoders E(h) (h=0, 1, 2, . . . , M)arranged in parallel between the switch 111 and the selector 112. TheM+1 error-correction encoders E(h) are encoders correspondingrespectively to information bit lengths from 0 bit to M bits. However,as will be described later, only the error-correction encoders E(0),E(1) and E(M) differ in function from others. The switch 111 and theselector 112 select one error-correction encoder corresponding to thedesignated bit length from the M+1 error-correction encoders E(j)according to the designated bit length k_(i) (k₀, k₁, . . . , k_(L-1))input from the information bit length switch 104. Each error-correctionencoder E generates an encoded bit sequence by performing a matrixoperation with the generator matrix. A typical example of theerror-correction encoder E is shown in FIG. 4.

As illustrated in FIG. 4, each of the M+1 error-correction encoders E(j)has a register 121 that holds an input k-bit information bit sequence, amatrix multiplier 122, and a storage 123 that holds a previouslydesignated k×m generator matrix G_(k). The matrix multiplier 122multiplies the bit sequence held in the register 121 by the k×Mgenerator matrix G_(k) to output a M-bit code which is the encoded k-bitinput information.

1.3) Block Length Converter

The block length converter 102 stores the encoded bit sequence inputfrom the variable information-length encoder 101 in a predeterminedarray in a memory, and converts the block length M to the code length Lof the Polar converter 103. As an example, as shown in FIG. 5, a methodof converting an input block of a 16-bit length into an output block ofan 8-bit length is described. That is, by arranging the 16-bit inputblocks in the same bit order as shown in FIG. 5, an 8-bit output blockbecomes 8-bit data, each bit being located at the same bit position ofeach input block. In this way, the block length converter 102 canrearrange the input bit block into an output bit sequence of a desiredbit length according to a certain rule.

1.4) Polar Converter

As illustrated in FIG. 6, the Polar converter 103 includes a register131 that holds an L-bit input bit sequence and a matrix multiplier 132.Assuming that a bit-reversal matrix B_(L) of size L is multiplied by anL×L matrix which is obtained by /−times Kronecker product of 2×2 matrixG₂

$\begin{matrix}{G_{2} = \begin{pmatrix}1 & 0 \\1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 1} \rbrack\end{matrix}$

to obtain a matrix product

[Math. 2]

B _(L) G ₂ ^(⊗l)  (1),

the matrix multiplier 132 multiplies the bit sequence held in theregister 131 by the above expression (1) to generate and output an L-bitcode by Polar encoding (note that L=2^(j)).

1.5) Information Bit Length Switch

As illustrated in FIG. 7, the information bit switch 104 has afrozen-bit position information generator 141 and a division bit lengthgenerator 142. The frozen-bit position information generator 141receives the code bit length M×L and the information bit length K tocalculate the frozen-bit position information of Polar encoding by whichthe information bit sequence of K-bit length is encoded as a code bitsequence of (M×L)-bit length. The division bit length generator 142generates L designated bit lengths (k₀, k₁, . . . , k_(L-1)) using thefrozen bit position information and the number L of divisions. Forexample, the division bit length generator 142, for each of i=0, 1, . .. , L−1, counts the number of integers at positions other thanfrozen-bit positions in the set of integers {iM, iM+1, . . . , (i+1)M−1}, and sets the count value as a designated bit length k_(i). In thePolar encoding scheme, by setting the designated bit length k_(i) asdescribed above, it is possible to allocate information bits to k_(i)communication channels of high error tolerance with excludingcommunication channels of low tolerance as frozen bits.

1.6) Variable Information-Length Decoder

As illustrated in FIG. 8, the variable information-length decoder 203includes M+1 error-correction decoders D (h) (h=0, 1, 2, . . . , M)arranged in parallel between the switch 211 and the selector 212. TheM+1 error-correction decoders D(h) differ from each other in the numberof information bits corresponding to an input signal sequence, theerror-correction decoders D(h) corresponding respectively to theerror-correction encoders E(h) of the encoding apparatus 100. The switch211 and the selector 212 select one error-correction decodercorresponding to the designated bit length from the M+1 error-correctiondecoders D(h) according to the designated bit length k_(i) (k₀, k₁, . .. , k_(L-1)) input from the information bit length switch 204. Eacherror-correction decoder D uses Viterbi decoding algorithm to generate acode bit sequence and an information bit sequence, and outputs theinformation bit sequence to the selector 212 and the code bit sequenceto the switch 211. As described later, the code bit output from eacherror-correction decoder D is fed back to the M Polar decoders P-DEC(j)through the switch 211. A typical example of the error-correctiondecoder D is shown in FIG. 8.

As illustrated in FIG. 9, each of the M+1 error-correction decoders D(h)includes a code trellis information storage 221, a branch metriccalculator 222, a path metric calculator 223, and a path metric selector224. The branch metric calculator 222, the path metric calculator 223and the path metric selector 224 perform metric calculation and bestmetric selection with reference to the code trellis information storedin the code trellis information storage 221. The branch metriccalculator 222 calculates the branch metric from the input signalsequence, the path metric calculator 223 calculates the path metric fromthe branch metric, and the path metric selector 224 selects the maximumlikelihood path metric from the calculated path metrics and thencalculates and outputs the code bit sequence and the information bitsequence corresponding to the maximum likelihood path metric. A specificexample will be described later.

2. Operation 2.1) Encoding Operation

As illustrated in FIG. 10, it is assumed that the encoding device 100inputs an information bit sequence of K bit length and output a code bitsequence of M×L bit length. It is also assumed that the K-bitinformation bit sequence is divided into L blocks each having blocklengths of 0 bits or more (including 0 bits) and M bits or lessaccording to a designated bit length k₀, k₁, . . . , k_(L-1)corresponding to channel polarization. That is, 0=<k_(i)=<M for i=0, 1,. . . , L−1. The L designated bit lengths k₀, k₁, . . . , k_(L-1) areheld in the information bit length switch 104 and supplied to thevariable information-length encoder 101.

When the bit length k_(i) is designated by the information bit lengthswitching signal (operation S301), the variable information-lengthencoder 101 causes the switch 110 and the selector 111 to select theencoder E (k_(i)) corresponding to the designated bit length k_(i). Theselected encoder E (k_(i)) generates a code block Bi of M-bit lengthfrom the same number of information bits as the designated bit lengthk_(i). The variable information-length encoder 101 performs the encodingoperation L times from i=0 to L−1 (operation S302), and thereby outputsthe L M-bit code blocks B₀ to B_(L-1) to the block length converter 102.

However, the encoder E(0), which is selected when k_(i)=0, outputs asequence 000 . . . 0 consisting of M 0s as triggered by the informationbit length switching signal. The encoder E(1), which is selected whenk_(i)=1, outputs the input 1 bit of information M times repeatedly astriggered by the information bit length switching signal. The encoderE(M), which is selected when k_(i)=M, outputs the input M-bitinformation sequence as it is. In other cases (k_(i)=2, 3, . . . M−1),the encoder E(k_(i)) selected in each case multiplies the relevant k_(i)bit information by the k×M generator matrix G_(k), and outputs theresult as an M-bit code block.

When the block length converter 102 inputs the L M-bit code blocks B₀ toB_(L-1), converts them into M L-bit blocks BL₀ to BL_(M-1) according toa predetermined rule, and output the results to the Polar converter 103.(Operation S303). For example, as illustrated in FIG. 5, L M-bit codeblocks B₀ to B_(L-1) are arranged in the same bit order, and L bits atthe same bit positions of the L code blocks B₀ to B_(L-1) aresequentially read out, thereby obtaining M L-bit blocks B_(L0) toBL_(M-1).

The Polar converter 103 sequentially inputs M L-bit blocks BL₀ toBL_(M-1) and sequentially outputs M L-bit code data C₀ to C_(M-1).Assuming that its input is an L-dimensional row vector u, the Polarconverter 103 multiplies the row vector u by the L×L matrix shown inExpression (1) to obtain an L-dimensional row vector c:

c=uB _(L) G ₂ ^(⊗l).  [Math. 3]

In this way, the Polar converter 103 generates the above-mentionedL-dimensional row vector c for all of the M L-bit blocks BL₀ toBL_(M-1), and outputs (M×L)-bit code data C₀ to C_(M-1) as a code bitsequence of the encoding device 100.

2.2) Decoding Operation

The decoding device 200 inputs the signal sequence corresponding to the(M×L)-bit code bit sequence output by the encoding device 100 throughthe transmission channel or the memory medium. This input signalsequence is represented by a sequence of log-likelihood ratioscorresponding to the code bits output by the encoding apparatus 100.Hereinafter, the logarithmic likelihood ratio at the input sidecorresponding to 1 bit at the output side is represented by m bits.Therefore, the number of bits of the input signal sequence of thedecoding device 200 is m×M×L (hereinafter referred to as mML). For thesake of simplicity, the decoding operation using the SC decoding methodwill be described. The same can be applied to the case of the SC-Listdecoding method.

<Polar Decoding>

As illustrated in FIG. 11, an input signal sequence of mML bit length isdivided by the switch 201 for each of mL bits, which are inputrespectively to M polar decoders P-DEC(0) to P-DEC(M−1). The M mL-bitlog-likelihood ratios correspond respectively to the L-bit codes C₀ toC_(M-1) output by the Polar converter 103 of the encoding device 100.The M polar decoders P-DEC(0) to P-DEC(M−1) input M mL-bit inputsignals, respectively, and sequentially output corresponding mL-bitlog-likelihood ratio values using the Polar code decoding method(operation S401). More specifically, each Polar decoder P-DECsequentially outputs the mL-bit log-likelihood ratio data every m bitsin L times. Hereinafter, each of the L m-bit data which is the output ofthe Polar decoder is distinguished in the output order i (=0, 1, . . . ,L−1). The information on the output order i is supplied from theinformation-length switch 204, as in the encoding device 100.

In the SC decoding method or SC-List decoding method described above, itis necessary to feed 1-bit data back to a corresponding Polar decoderevery time m-bit log-likelihood ratio data is output. According to thisembodiment, the feedback data is generated by the variableinformation-length decoder 203 in the subsequent stage.

The i-th m-bit data output from each of the M Polar decoders P-DEC(0) toP-DEC(M−1) is combined through the multiplexer/demultiplexer 202 and themM bit data is output to the variable information-length decoder 203.The variable information-length decoder 203 generates a k_(i)-bitinformation bit sequence corresponding to the mM bit data and M-bit codedata corresponding to this k_(i)-bit information bit sequence accordingto Viterbi decoding as described later (operation S402). For example, aswill be described later, a part of the M-bit code data becomes ak_(i)-bit information bit sequence. The information bit sequence ofk_(i) bits becomes the output of the decoding device 200, the M-bit codedata is demultiplexed through the multiplexer/demultiplexer 202, andeach bit is fed back to the corresponding Polar decoder P-DEC.

More specifically, in the case of i<L−1, the multiplexer/demultiplexer202 demultiplexes the M-bit code generated by the variableinformation-length decoder 203 in 1-bit units, and each bit is fed backto the corresponding Polar decoder P-DEC. The Polar decoder P-DECcalculates the (i+1)-th m-bit data using the fed back 1-bit data.Similarly, the above decoding process is repeated until i=L−1. Finally,the information bit sequence of a total of K (=k₀+k₁+ . . . +k_(L-1))bits is obtained.

<Variable Information-Length Decoding>

The operation of the variable information-length decoder 203 will bedescribed. In principle, as shown in FIG. 8, the switch 211 and theselector 212 select one decoder from M+1 decoders D(0) to D(M) accordingto the information bit length switching signal input from theinformation-length switch 204. The decoder D(k_(i)) generates ak_(i)-bit information bit sequence and a corresponding M-bit code bitsequence, outputs the k_(i)-bit information through the selector 212,and feeds the M-bit code back to the Polar decoder side through theswitch 211.

The M+1 decoders D(0) to D(M) correspond to the encoders E(0) to E(M) inthe variable information-length encoder 101 of the encoding device 100,respectively. Therefore, the decoder D(0) which is selected when k_(i)=0has no information bit from the selector 212, but feeds data “000 . . .0” consisting of M 0s back to the switch 211.

The decoder D(1) selected when k_(i)=1 compares the sum of the decodedsignals having a positive value and the sum of the decoded signalshaving a negative value with respect to the M Polar decoded signalsrepresented by the m-bit log-likelihood ratio. In accordance with thecomparison result, the decoder D(1) outputs 1-bit information of 0 or 1through the selector 212 and also returns an M-bit sequence 000 . . . 0or 111 . . . 1 as feedback data to the switch 211, wherein the M-bitsequence is obtained by repeating the generated 1 bit M times.

Further, the decoder D(M) selected when k_(i)=M determines whether eachof the M Polar decoded signals is positive or negative and generatesM-bit data. The decoder D(M) outputs it through the selector 212 andfeeds it back to the Polar decoder side through the switch 211.

In other cases (k_(i)=2, 3, . . . M−1), the decoder D(k_(i)) selected ineach case uses the Viterbi decoding algorithm, as described in FIG. 9,to generate M bit code and k_(i)-bit information and to output the k_(i)bit information to the selector 212 and the M-bit data as the feedbackdata to the switch 211.

According to the above-described decoding operation, the decoding device200 terminates the process at the time when the information bit sequenceof K bit length has been output from the input signal sequence of mMLbit length.

2.3) Effects

According to the exemplary embodiment of the present invention asdescribed above, M Polar decoding processes of bit length L can beperformed in parallel. Further, as described in the next exemplaryembodiment, the number of time steps required for the decoding processin the variable information-length decoder 203 using the Viterbialgorithm is M. Since the number of time steps required for the decodingprocess is M, the total number of time steps required for the decodingprocess is estimated as ML+L log₂L.

For example, assuming M=16 and L=64, decoding processing on a code bitsequence of a length of 1024 bits is performed. According to the presentexemplary embodiment, since the information bit is divided by using thesame channel polarization as that of the 1024-bit-length Polar code, theerror-correction capability is equal to or higher than that of theconventional Polar encoding/decoding method and the decoding process canbe completed in about 14% of the time steps.

3. Example

A specific operation of the above-described encoding device 100 anddecoding device 200 will be described. As an example, it is assumed thatthe number of information bits K=64 bits, the code bit length ML=128,the number of divisions L=8, and the error-correction code length M=16.There will be described the case where a 64-bit information bit sequenceis divided as k₀=0, k₁=2, k₂=4, k₃=11, k₄=5, k₅=12, k₆=14, k₇=16, thatis, K=0+2+4+11+5+12+14+16 based on channel polarization similar to theconventional 128-bit-length Polar code. As will be described below,according to the present example, it is possible to obtain anerror-correction capability equal to or higher than that of theconventional 128-bit-length Polar encoding/decoding method, and it isalso possible to complete the decoding process in about 17% of thenumber of time steps, compared to the conventional 128-bit-length Polarencoding/decoding method.

3.1) Encoding

Referring to FIG. 10, information bits of K=64 bits are divided intoeight blocks having different lengths (K=0+2+4+11+5+12+14+16). Eachblock is input to a corresponding encoder E in the variableinformation-length encoder 101, which outputs eight encoded bit blocksB₀ to B₇ of 16-bit length.

The variable information-length encoder 101 includes a total of 17(=M+1) types of encoders E as shown in FIG. 3, but in this example, onlyeight types of k=0, 2, 4, 11, 5, 12, 14 and 16 are used. As describedabove, in the case of k=0, a 16-bit length of 000 . . . 0 is output. Inthe case of k=16, the input is output as it is. Accordingly,substantially six types of encoders E(2), E(4), E(5), E(11), E(12),E(14) are required. As shown in FIG. 4, the encoder E multiplies thek-bit input information bit by the k×16 generator matrix G_(k).Therefore, in the present example, the following six generator matricesare used.

$\begin{matrix}{G_{2} = \begin{pmatrix}1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 4} \rbrack \\{G_{4} = \begin{pmatrix}1 & 1 & \; & \; & \; & \; & 1 & 1 & \; & \; & 1 & 1 & 1 & 1 & \; & \; \\\; & \; & 1 & 1 & \; & \; & 1 & 1 & \; & \; & 1 & 1 & \; & \; & 1 & 1 \\\; & \; & \; & \; & 1 & 1 & 1 & 1 & \; & \; & \; & \; & 1 & 1 & 1 & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 5} \rbrack \\{G_{5} = \begin{pmatrix}1 & \; & \; & 1 & \; & 1 & 1 & \; & \; & 1 & 1 & \; & 1 & \; & \; & 1 \\\; & 1 & \; & 1 & \; & 1 & \; & 1 & \; & 1 & \; & 1 & \; & 1 & \; & 1 \\\; & \; & 1 & 1 & \; & \; & 1 & 1 & \; & \; & 1 & 1 & \; & \; & 1 & 1 \\\; & \; & \; & \; & 1 & 1 & 1 & 1 & \; & \; & \; & \; & 1 & 1 & 1 & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 6} \rbrack \\{G_{11} = \begin{pmatrix}1 & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & 1 & 1 & 1 \\\; & 1 & \; & \; & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & 1 & \; & \; \\\; & \; & 1 & \; & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & 1 & \; \\\; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & 1 \\\; & \; & \; & \; & 1 & \; & \; & 1 & \; & \; & \; & \; & \; & 1 & 1 & \; \\\; & \; & \; & \; & \; & 1 & \; & 1 & \; & \; & \; & \; & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; & \; & \; & \; & \; & 1 & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & 1 & \; & 1 & 1 & \; \\\; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & 1 & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; & 1 & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 7} \rbrack \\{G_{12} = \begin{pmatrix}1 & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & 1 & \; & \; \\\; & 1 & \; & \; & \; & \; & \mspace{11mu} & 1 & \; & \; & \; & 1 & \; & 1 & \; & \; \\\; & \; & 1 & \; & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & 1 \\\; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & 1 \\\; & \; & \; & \; & 1 & \; & \; & 1 & \; & \; & \; & \; & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & 1 & \; & 1 & \; & \; & \; & \; & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & 1 & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \mspace{14mu} & \; & \; & \; & 1 & \; & 1 & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; & \; & \; \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 8} \rbrack \\{G_{14} = \begin{pmatrix}1 & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & 1 & \; & \; & \; & \; & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & 1 & \; & \; & \; & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & 1 & \; & \; & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & 1 & \; & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & \; & 1 & \; & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & \; & \; & 1 & 1 & \; & \; & \; & \; & \; & \; & \; & \; \\\; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & \; & \; & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & \; & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & \; & 1 \\\; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & \; & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 9} \rbrack\end{matrix}$

The eight 16-bit code blocks B₀ to B₇ as output of the variableinformation-length encoder 101 are converted in block length from 16 to8 by the block length converter 102. Specifically, as shown in FIG. 5,the input bit sequence is written in the memory in a horizontaldirection (16 bits for each row) and is read in the vertical direction(8 bits for each column). The 16 8-bit sequences whose bit order hasbeen changed in this way are sequentially output to the Polar converter103.

As illustrated in FIG. 6, the Polar converter 103 multiplies 8-bit inputinformation by an 8×8 matrix shown below and outputs an 8-bit code. ThePolar converter 103 sequentially outputs 16 8-bit codes and thenterminates the encoding process.

$\begin{matrix}{{B_{8}G_{2}^{\otimes 3}} = \begin{pmatrix}1 & \; & \; & \; & \; & \; & \; & \; \\1 & \; & \; & \; & 1 & \; & \; & \; \\1 & \; & 1 & \; & \; & \; & \; & \; \\1 & \; & 1 & \; & 1 & \; & 1 & \; \\1 & 1 & \; & \; & \; & \; & \; & \; \\1 & 1 & \; & \; & 1 & 1 & \; & \; \\1 & 1 & 1 & 1 & \; & \; & \; & \; \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\end{pmatrix}} & \lbrack {{Math}.\mspace{14mu} 10} \rbrack\end{matrix}$

3.2) Decoding

The decoding device 200 inputs the signal sequence corresponding to ML(=128)-bit code sequence which is the output of the encoding device 100.In the case where each input signal is quantized in 9 (=m) bitsincluding 1 bit representing positive or negative, the number of inputbits to the decoding device 200 is 1152 (=128×9=ML×m) bits. By dividingthis input signal sequence in units of 72 (=8×9=L×m) bits from thebeginning into 16 divisions, the 16 division signal sequences are inputto 16 Polar decoders P-DEC(0) to P-DEC(15), respectively.

The Polar decoder P-DEC uses the existing Polar decoding techniqueexcept for the generation of the feedback data required for each outputdata, and thus the description thereof will be omitted. Hereinafter, thevariable information-length decoder 203 for generating feedback data anddecoding output will be described.

As shown in FIG. 8, the variable information-length decoder 203 isprovided with a total of 17 (=M+1) types of decoders D in principle, butin this example, only eight types of k=0, 2, 4, 11, 5, 12, 14, and 16are used. As described above, since the cases of k=0 and k=16 do notmatter, as in the case of the encoding apparatus 100, the six types ofdecoders D(2), D(4), D(5), D(11), D(12) and D(14) are substantiallyrequired. These six types of decoders D hold trellis codes correspondingrespectively to the generator matrices G₂, G₄, G₅, G₁₁, G₁₂, and G₁₄ inthe above six types of encoders E and outputs the information bitsequence and the code bit sequence by applying the Viterbi algorithm.

FIGS. 12 to 17 show six types of code-trellis corresponding to thegenerator matrices G₂, G₄, G₅, G₁₁, G₁₂, and G₁₄, respectively. However,the labels a, b, e, f, g, h labeled respectively on the branches in FIG.15 indicate eight sets consisting of two 4-bit data as shown below.

$\begin{matrix}{{{a = \{ {0000,1111} \}}{b = \{ {0011,1100} \}}c = \{ {0101,1010} \}}{d = \{ {0110,1001} \}}{e = \{ {0001,1110} \}}{f = \{ {0010,1101} \}}{g = \{ {0100,1011} \}}{h = \{ {1000,0111} \}}} & \lbrack {{Math}.\mspace{14mu} 11} \rbrack\end{matrix}$

In addition, the labels shown on the branches in FIG. 16 represent theunion of two sets selected from the above-described eight sets. Forinstance,

a+b={0000,1111,0011,1100}.  [Math. 12]

As with the above, other cases are processed.

Furthermore, the labels shown on the branches in FIG. 17 represent theunion of four sets selected from the above eight sets. For instance,

a+b+c+d={0000,1111,0011,1100,0101,1010,0110,1001}.  [Math. 13]

As with the above, other cases are processed.

As described above, each of the branches in the trellis diagrams shownin FIGS. 12, 13 and 14 corresponds to one 4-bit label shown in thefigures. The trellis shown in FIG. 15 corresponds to two 4-bit labels,the trellis shown in FIG. 16 to four 4-bit labels, and the trellis shownin FIG. 17 to eight 4-bit labels. In either case, the processing for 4bits in unit-time step can be performed and accordingly the decodingprocess is completed in 4 unit-time steps at the shortest.

In each decoder D, the Viterbi algorithm based on each code-trellis isapplied to the input signal sequence to calculate the maximum likelihoodpath. The maximum likelihood path can be calculated in 4 time units atthe shortest as described above. The maximum likelihood path is composedof four branches and a corresponding information bit sequence of k bitsis output. Further, a 16-bit sequence composed of the labels of fourbranches that are also the maximum likelihood path is fed as a code bitsequence back to the Polar decoder P-DEC.

The example of the decoding device 200 has been described abovecentering on the variable information-length decoder 203 and the decoderD that is a component thereof. Although the case where the Viterbialgorithm using code-trellis is used has been described as aconfiguration example of the decoder D, the use of the Viterbi algorithmis just one example and the present invention is not limited to thisexample. In particular, assuming that SC-List decoding is used in thePolar decoder P-DEC, a list Viterbi algorithm or another list decodingmethod matching the SC-List decoding can be used to guarantee at leastthe same level of error-correction capability as the conventional Polarcode and decoding method.

4. Other Exemplary Embodiments

The above-described encoding device 100 and decoding device 200 may eachbe a single device, or both may be incorporated in a single dataprocessing device. Further, the encoder/decoder may be configured on asingle chip. Further, each function of the encoding device 100 and thedecoding device 200 can also be implemented by executing a computerprogram on a processor. Such a program or a storage device storing theprogram is also included in the technical scope of the presentinvention.

As illustrated in FIG. 18, it is assumed that the data processing device500 includes a processor 501, an interface 502 for exchanging data withoutside, and a memory 503 for storing programs and the like. Theprocessor 501 functions as the encoding device 100 and/or the decodingdevice 200 by executing the programs that realizes the above-describedencoding function and/or decoding function from the memory 503. Such adata processing device 500 can be used as the encoder and the decoder ofa communication device or a data writing/reading device.

5. Supplementary Note

Part or all of the above-described exemplary embodiments may bedescribed as, but not limited to, the following supplementary notes.

(Supplementary Note 1)

An encoding device that encodes an information bit sequence blocked intoblocks of a constant bit length K to generate a code bit sequence of aconstant bit length M×L, the encoding device comprising:

an error-correction encoding means that inputs the information bitsequence on division for each designated bit length according to aninformation-bit length switching signal and performs error-correctionencoding on an information block of the designated bit length togenerate L M-bit codes, each M-bit code having a predetermined bitlength M;

a block length conversion means that converts the L M-bit codes into ML-bit blocks each having a predetermined bit length of L by reorderingbits of the L M-bit codes;

a Polar conversion means that converts the M L-bit blocks to M L-bitcodes, each L-bit code having a bit length of L, through channelpolarization processing to output a converted M×L-bit code as the codebit sequence; and

an information bit length switching means that generates the informationbit length switching signal for dividing the information bit sequenceinto L designated bit lengths which are not necessarily constant, basedon channel polarization information of the Polar conversion means.

(Supplementary Note 2)

The encoding device according to supplementary note 1, wherein theinformation bit length switching means sets the designated bit length asa count of integers at positions other than frozen-bit positions of thechannel polarization in a set of integers {iM, iM+1, . . . , (i+1) M−1}for each i for I=0, 1, . . . , L−1.

(Supplementary Note 3)

The encoding device according to supplementary note 1 or 2, wherein theerror-correction encoding means comprises:

M+1 error-correction encoders each inputting different designated bitlengths k (k is an integer equal to or greater than 0 and equal to orsmaller than M); and

a selection means that selects one from the M+1 error-correctionencoders according to the information bit length switching signal,

wherein each of the M+1 error-correction encoders adds redundant bits toan information bit block of the designated bit length k to generateM-bit code, and the selection means selectively switches anerror-correction encoder depending on the designated bit length kcorresponding to the information bit length switching signal.

(Supplementary Note 4)

A decoding device that inputs an input signal sequence and estimates aninformation bit sequence from the input signal sequence, the inputsignal sequence corresponding to a code bit sequence of a constant bitlength M×L, wherein an encoding device generates the code bit sequencethrough error-correction encoding and channel polarization processing onan information bit sequence of a constant bit length K, the decodingdevice comprising:

M Polar decoding means that divides the input signal sequence into Minput signal blocks, each input signal block including L input signals,performs the channel polarization processing on each of the M inputsignal blocks, and outputs L Polar decoded signals for each of the Minput signal blocks;

an error-correction decoding means that inputs a Polar decoded signalaccording to a designated bit length designated by an information bitlength switching signal, from M Polar decoded signal blocks, each Polardecoded signal block including L Polar decoded signals which are outputrespectively by the M Polar decoding means, and estimates theinformation bit sequence according to error-correction decoding scheme;and

an information bit length switching means that generates the informationbit length switching signal for designating, as the designated bitlength, an information bit length included in the M Polar decoded signalblocks output respectively by the M Polar decoding means.

(Supplementary Note 5)

The decoding device according to supplementary note 4, wherein theinformation bit length switching means sets the designated bit length asa count of integers at positions other than frozen-bit positions in aPolar encoding scheme corresponding to the Polar decoding means, in aset of integers {iM, iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . .. , L−1.

(Supplementary Note 6)

The decoding device according to supplementary note 4 or 5, wherein theerror-correction decoding means comprises:

M+1 error-correction decoders each outputting different designated bitlengths k (k is an integer equal to or greater than 0 and equal to orsmaller than M); and

a selection means that selects one from the M+1 error-correctiondecoders according to the information bit length switching signal,

wherein the M+1 error-correction decoders correspond respectively to M+1error-correction encoders which generate M-bit codes by adding redundantbits to information bit blocks of designated bit lengths, and theselection means selectively switches an error-correction decoderdepending on the designated bit length corresponding to the informationbit length switching signal.

(Supplementary Note 7)

The decoding device according to supplementary note 6, wherein the M+1error-correction decoders comprises:

a storage means that stores code-trellis information whose size isdetermined by a k×M generator matrix, wherein a designated bit length kis an integer equal to or greater than 0 and equal to or smaller than M;and

a calculation means that estimates an information bit sequence of a bitlength k according to Viterbi algorithm using the code-trellisinformation.

(Supplementary Note 8)

The decoding device according to one of supplementary notes 4-7, whereinthe error-correction decoding means feeds code bits of a code bitsequence back to the M Polar decoding means for Polar decoding,respectively, the code bit sequence corresponding to the information bitsequence decoded in the M+1 error-correction decoders.

(Supplementary Note 9)

An encoding method for encoding an information bit sequence blocked intoblocks of a constant bit length K to generate a code bit sequence of aconstant bit length M×L, the encoding method comprising:

by an error-correction encoding means, inputting the information bitsequence on division for each designated bit length according to aninformation-bit length switching signal and performing error-correctionencoding on an information block of the designated bit length togenerate L M-bit codes, each M-bit code having a predetermined bitlength M;

by a block length conversion means, converting the L M-bit codes into ML-bit blocks each having a predetermined bit length of L by reorderingbits of the L M-bit codes;

by a Polar conversion means, converting the M L-bit blocks to M L-bitcodes, each L-bit code having a bit length of L, through channelpolarization processing to output a converted M×L-bit code as the codebit sequence; and

by an information bit length switching means, generating the informationbit length switching signal for dividing the information bit sequenceinto L designated bit lengths which are not necessarily constant, basedon channel polarization information of the Polar conversion means.

(Supplementary Note 10)

The encoding method according to supplementary note 8, wherein theinformation bit length switching means sets the designated bit length asa count of integers at positions other than frozen-bit positions of thechannel polarization in a set of integers {iM, iM+1, . . . , (i+1) M−1}for each i for I=0, 1, . . . , L−1.

(Supplementary Note 11)

The encoding method according to supplementary note 8 or 9, wherein theerror-correction encoding means selects one from M+1 error-correctionencoders according to the information bit length switching signal, theM+1 error-correction encoders each inputting different designated bitlengths k (k is an integer equal to or greater than 0 and equal to orsmaller than M); and

each of the M+1 error-correction encoders adds redundant bits to aninformation bit block of the designated bit length k to generate M-bitcode, and selectively switches an error-correction encoder depending onthe designated bit length k corresponding to the information bit lengthswitching signal.

(Supplementary Note 12)

A decoding method for inputting an input signal sequence and estimatingan information bit sequence from the input signal sequence, the inputsignal sequence corresponding to a code bit sequence of a constant bitlength M×L, wherein an encoding device generates the code bit sequencethrough error-correction encoding and channel polarization processing onan information bit sequence of a constant bit length K, the decodingmethod comprising:

by M Polar decoding means, dividing the input signal sequence into Minput signal blocks, each input signal block including L input signals,performing the channel polarization processing on each of the M inputsignal blocks, and outputting L Polar decoded signals for each of the Minput signal blocks;

by an error-correction decoding means, inputting a Polar decoded signalaccording to a designated bit length designated by an information bitlength switching signal, from M Polar decoded signal blocks, each Polardecoded signal block including L Polar decoded signals which are outputrespectively by the M Polar decoding means, and estimating theinformation bit sequence according to error-correction decoding scheme;and

by an information bit length switching means, generating the informationbit length switching signal for designating, as the designated bitlength, an information bit length included in the M Polar decoded signalblocks output respectively by the M Polar decoding means.

(Supplementary Note 13)

The decoding method according to supplementary note 12, wherein theinformation bit length switching means sets the designated bit length asa count of integers at positions other than frozen-bit positions in aPolar encoding scheme corresponding to the Polar decoding means, in aset of integers {iM, iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . .. , L−1.

(Supplementary Note 14)

The decoding method according to supplementary note 12 or 13, whereinthe error-correction decoding means selects one from M+1error-correction decoders according to the information bit lengthswitching signal, the M+1 error-correction decoders each outputtingdifferent designated bit lengths k (k is an integer equal to or greaterthan 0 and equal to or smaller than M);

the M+1 error-correction decoders correspond respectively to M+1error-correction encoders which generate M-bit codes by adding redundantbits to information bit blocks of designated bit lengths; and

the selection means selectively switches an error-correction decoderdepending on the designated bit length corresponding to the informationbit length switching signal.

(Supplementary Note 15)

The decoding method according to supplementary note 14, wherein the M+1error-correction decoders:

stores code-trellis information whose size is determined by a k×Mgenerator matrix, wherein a designated bit length k is an integer equalto or greater than 0 and equal to or smaller than M; and

estimates an information bit sequence of a bit length k according toViterbi algorithm using the code-trellis information.

(Supplementary Note 16)

The decoding method according to one of supplementary notes 12-15,wherein the error-correction decoding means feeds code bits of a codebit sequence back to the M Polar decoding means for Polar decoding,respectively, the code bit sequence corresponding to the information bitsequence decoded in the M+1 error-correction decoders.

(Supplementary Note 17)

A program that causes a computer to function as an encoding device thatencodes an information bit sequence blocked into blocks of a constantbit length K to generate a code bit sequence of a constant bit lengthM×L, the program comprising:

an error-correction encoding function of inputting the information bitsequence on division for each designated bit length according to aninformation-bit length switching signal and performs error-correctionencoding on an information block of the designated bit length togenerate L M-bit codes, each M-bit code having a predetermined bitlength M;

a block length conversion function of converting the L M-bit codes intoM L-bit blocks each having a predetermined bit length of L by reorderingbits of the L M-bit codes;

a Polar conversion function of converting the M L-bit blocks to M L-bitcodes, each L-bit code having a bit length of L, through channelpolarization processing to output a converted M×L-bit code as the codebit sequence; and

an information bit length switching function of generating theinformation bit length switching signal for dividing the information bitsequence into L designated bit lengths which are not necessarilyconstant, based on channel polarization information of the Polarconversion means.

(Supplementary Note 18)

A program that causes a computer to function as an decoding device thatinputs an input signal sequence and estimates an information bitsequence from the input signal sequence, the input signal sequencecorresponding to a code bit sequence of a constant bit length M×L,wherein an encoding device generates the code bit sequence througherror-correction encoding and channel polarization processing on aninformation bit sequence of a constant bit length K, the programcomprising:

M Polar decoding functions of dividing the input signal sequence into Minput signal blocks, each input signal block including L input signals,of performing the channel polarization processing on each of the M inputsignal blocks, and of outputting L Polar decoded signals for each of theM input signal blocks;

an error-correction decoding function of inputting a Polar decodedsignal according to a designated bit length designated by an informationbit length switching signal, from M Polar decoded signal blocks, eachPolar decoded signal block including L Polar decoded signals which areoutput respectively by the M Polar decoding means, and estimating theinformation bit sequence according to error-correction decoding scheme;and

an information bit length switching function of generating theinformation bit length switching signal for designating, as thedesignated bit length, an information bit length included in the M Polardecoded signal blocks output respectively by the M Polar decoding means.

(Supplementary Note 19)

A data processing device comprising: an encoding device according to oneof supplementary notes 1-3; and a decoding device according to one ofsupplementary notes 4-8.

(Supplementary Note 20)

A communication apparatus comprising the data processing deviceaccording to supplementary note 19.

(Supplementary Note 21)

A data writing/reading apparatus comprising the data processing deviceaccording to supplementary note 19.

INDUSTRIAL APPLICABILITY

The present invention is applicable to an encoding device and a decodingdevice in a system in which bit errors may occur in digital data due todisturbance such as noises.

-   100 Encoder-   101 Variable information-length encoder-   102 Block length converter-   103 Polar converter-   104 Division bit length switch-   111 Switch-   112 Selector-   121 Register-   122 Matrix multiplier-   123 k×M generator matrix-   131 Register-   132 Matrix multiplier-   141 Frozen-bit position information generator-   142 Division bit length generator-   200 Decoding device-   201 Switch-   202 Multiplexer/demultiplexer-   203 Variable information-length decoder-   204 Information bit length switch-   211 Switch-   212 Selector-   221 Code-trellis information storage-   222 Branch metric calculator-   223 Path metric calculator-   224 Path metric selector-   500 Data processing device-   501 Processor-   502 Interface-   503 Memory

1. An encoding device that encodes an information bit sequence of aconstant bit length K to generate a code bit sequence of a constant bitlength M×L, the encoding device comprising: a variableinformation-length encoder configured to: input the information bitsequence; divide the information bit sequence into L information blocksof designated bit lengths according to an information-bit lengthswitching signal; and perform error-correction encoding on each of the Linformation blocks to generate L M-bit codes; a block length converterthat converts the L M-bit codes into M L-bit blocks by reordering bitsof the L M-bit codes; a Polar converter that converts the M L-bit blocksto M L-bit codes through channel polarization processing to output aconverted M×L-bit code as the code bit sequence; and an information bitlength switch that generates the information bit length switching signalfor dividing the information bit sequence into L designated bit lengthswhich are not necessarily constant, based on channel polarizationinformation of the Polar converter.
 2. The encoding device according toclaim 1, wherein the information bit length switch sets the designatedbit lengths as a count of integers at positions other than frozen-bitpositions of the channel polarization in a set of integers {iM, iM+1, .. . , (i+1) M−1} for each i for I=0, 1, . . . , L−1.
 3. The encodingdevice according to claim 1, wherein the variable information-lengthencoder comprises: M+1 error-correction encoders each inputtingdifferent designated bit lengths k (k is an integer equal to or greaterthan 0 and equal to or smaller than M); and a selector that selects onefrom the M+1 error-correction encoders according to the information bitlength switching signal, wherein each of the M+1 error-correctionencoders adds redundant bits to an information bit block of acorresponding designated bit length k to generate an M-bit code, and theselector selectively switches an error-correction encoder depending onthe designated bit length k corresponding to the information bit lengthswitching signal.
 4. A decoding device that inputs an input signalsequence and decodes an information bit sequence from the input signalsequence, the input signal sequence corresponding to a code bit sequenceof a constant bit length M×L, wherein an encoding device generates thecode bit sequence through error-correction encoding and channelpolarization processing on an information bit sequence of a constant bitlength K, the decoding device comprising: M Polar decoders configuredto: divide the input signal sequence into M input signal blocks, eachinput signal block including L input signals; performs the channelpolarization processing on each of the M input signal blocks; andoutputs L Polar decoded signals for each of the M input signal blocks; avariable information-length decoder configured to: input a Polar decodedsignal according to a designated bit length designated by an informationbit length switching signal, from M Polar decoded signal blocks, eachPolar decoded signal block including L Polar decoded signals which areoutput respectively by the M Polar decoders; and estimate theinformation bit sequence according to error-correction decoding scheme;and an information bit length switch that generates the information bitlength switching signal for designating, as the designated bit lengths,information bit lengths included in the M Polar decoded signal blocksoutput respectively by the M Polar decoders.
 5. The decoding deviceaccording to claim 4, wherein the information bit length switch sets thedesignated bit length as a count of integers at positions other thanfrozen-bit positions in a Polar encoding scheme corresponding to thePolar decoders, in a set of integers {iM, iM+1, . . . , (i+1) M−1} foreach i for I=0, 1, . . . , L−1.
 6. The decoding device according toclaim 4, wherein the variable information-length decoder comprises: M+1error-correction decoders each outputting different designated bitlengths k (k is an integer equal to or greater than 0 and equal to orsmaller than M); and a selector that selects one from the M+1error-correction decoders according to the information bit lengthswitching signal, wherein the M+1 error-correction decoders correspondrespectively to M+1 error-correction encoders which generate M-bit codesby adding redundant bits to information bit blocks of designated bitlengths, and the selector selectively switches an error-correctiondecoder depending on the designated bit length corresponding to theinformation bit length switching signal.
 7. The decoding deviceaccording to claim 6, wherein the M+1 error-correction decoderscomprises: a storage that stores code-trellis information whose size isdetermined by a k×M generator matrix, wherein a designated bit length kis an integer equal to or greater than 0 and equal to or smaller than M;and a calculator configured to estimate an information bit sequence of abit length k according to Viterbi algorithm using the code-trellisinformation.
 8. The decoding device according to claim 4, wherein theerror-correction decoders feeds code bits of a code bit sequence back tothe M Polar decoding means for Polar decoding, respectively, the codebit sequence corresponding to the information bit sequence decoded inthe M+1 error-correction decoders.
 9. An encoding method for encoding aninformation bit sequence of a constant bit length K, to generate a codebit sequence of a constant bit length M×L, the encoding methodcomprising: by a variable information-length encoder, inputting theinformation bit sequence; dividing the information bit sequence into Linformation blocks of designated bit lengths according to aninformation-bit length switching signal; and performing error-correctionencoding on each of the L information blocks to generate L M-bit codes;by a block length converter, converting the L M-bit codes into M L-bitblocks by reordering bits of the L M-bit codes; by a Polar converter,converting the M L-bit blocks to M L-bit codes through channelpolarization processing to output a converted M×L-bit code as the codebit sequence; and by an information bit length switch, generating theinformation bit length switching signal for dividing the information bitsequence into L designated bit lengths which are not necessarilyconstant, based on channel polarization information of the Polarconverter.
 10. The encoding method according to claim 9, wherein theinformation bit length switch sets the designated bit length as a countof integers at positions other than frozen-bit positions of the channelpolarization in a set of integers {iM, iM+1, . . . , (i+1) M−1} for eachi for I=0, 1, . . . , L−1.
 11. The encoding method according to claim 9,wherein the variable information-length encoder selects one from M+1error-correction encoders according to the information bit lengthswitching signal, the M+1 error-correction encoders each inputtingdifferent designated bit lengths k (k is an integer equal to or greaterthan 0 and equal to or smaller than M); and each of the M+1error-correction encoders adds redundant bits to an information bitblock of a corresponding designated bit length k to generate M-bit code,and selectively switches an error-correction encoder depending on thedesignated bit length k corresponding to the information bit lengthswitching signal.
 12. A decoding method for inputting an input signalsequence and decoding an information bit sequence from the input signalsequence, the input signal sequence corresponding to a code bit sequenceof a constant bit length M×L, wherein an encoding device generates thecode bit sequence through error-correction encoding and channelpolarization processing on an information bit sequence of a constant bitlength K, the decoding method comprising: by M Polar decoders, dividingthe input signal sequence into M input signal blocks, each input signalblock including L input signals, performing the channel polarizationprocessing on each of the M input signal blocks, and outputting L Polardecoded signals for each of the M input signal blocks; by a variableinformation-length decoder, inputting a Polar decoded signal accordingto a designated bit length designated by an information bit lengthswitching signal, from M Polar decoded signal blocks, each Polar decodedsignal block including L Polar decoded signals which are outputrespectively by the M Polar decoders, and estimating the information bitsequence according to error-correction decoding scheme; and by aninformation bit length switch, generating the information bit lengthswitching signal for designating, as the designated bit length, aninformation bit length included in the M Polar decoded signal blocksoutput respectively by the M Polar decoders.
 13. The decoding methodaccording to claim 12, wherein the information bit length switch setsthe designated bit length as a count of integers at positions other thanfrozen-bit positions in a Polar encoding scheme corresponding to thePolar decoding means, in a set of integers {iM+1, . . . , (i+1) M−1} foreach i for I=0, 1, . . . , L−1.
 14. The decoding method according toclaim 12, wherein the variable information-length decoder selects onefrom M+1 error-correction decoders according to the information bitlength switching signal, the M+1 error-correction decoders eachoutputting different designated bit lengths k (k is an integer equal toor greater than 0 and equal to or smaller than M); the M+1error-correction decoders correspond respectively to M+1error-correction encoders which generate M-bit codes by adding redundantbits to information bit blocks of designated bit lengths; and anerror-correction decoder is selectively switched depending on thedesignated bit length corresponding to the information bit lengthswitching signal.
 15. The decoding method according to claim 14, whereinat each of the M+1 error-correction decoders, storing code-trellisinformation whose size is determined by a k×M generator matrix, whereina designated bit length k is an integer equal to or greater than 0 andequal to or smaller than M; and estimating an information bit sequenceof a bit length k according to Viterbi algorithm using the code-trellisinformation.
 16. The decoding method according to claim 12, wherein thevariable information-length decoder feeds code bits of a code bitsequence back to the M Polar decoding means for Polar decoding,respectively, the code bit sequence corresponding to the information bitsequence decoded in the M+1 error-correction decoders.
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